Japanese Patent Application Laid-Open Publication No. H6-151639 (Patent Document 1) discloses a semiconductor device in which a ground pin and a power pin among a plurality of pins (terminals) of a wiring substrate are continuously disposed in series from an inside to an outside.
Further, Japanese Patent Application Laid-Open Publication No. 2006-237385 (Patent Document 2) and Japanese Patent Application Laid-Open Publication No. 2007-213375 (Patent Document 3) disclose semiconductor devices in which a plurality of memory chips and a data processing chip which controls the plurality of memory chips are mounted side by side on a wiring substrate.